Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning

نویسندگان

چکیده

Microarchitectural timing channels enable unwanted information flow across security boundaries, violating fundamental assumptions. They leverage variations of several state-holding microarchitectural components and have been demonstrated instruction set architectures hardware implementations. Analogously to memory protection, (Ge et al. 2019) proposed time protection for preventing leakage via channels. also showed that time protection calls support. This work leverages the open extensible RISC-V architecture (ISA) introduce temporal fence fence.t , which provides required mechanisms by clearing vulnerable state guaranteeing a history-independent context-switch latency. We propose discuss three different implementations implement them on an experimental version seL4 microkernel (Klein 2014) CVA6, open-source, in-order, application class, 64-bit core (Zaruba Benini 2019). find complete, systematic, ISA-supported erasure all non-architectural is most effective implementation while featuring low effort, minimal performance overhead less than 1%, negligible costs.

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ژورنال

عنوان ژورنال: IEEE Transactions on Computers

سال: 2023

ISSN: ['1557-9956', '2326-3814', '0018-9340']

DOI: https://doi.org/10.1109/tc.2022.3212636